Address Generation Unit Using Nested Loops To Scan Multi-Dimensional Data Structures

ABSTRACT

An apparatus, system, and method in accordance with the invention may include providing a multi-dimensional data structure and providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining the characteristics of the nested loops. The method may then include accessing the data structure at the real addresses calculated by the address generation unit.

BACKGROUND

This invention relates to data processing, and more particularly to address generation units using nested loops to scan multi-dimensional data structures.

Signal and media processing (also referred to herein as “data processing”) is pervasive in today's electronic devices. This is true for cell phones, media players, personal digital assistants, gaming devices, personal computers, home gateway devices, and a host of other devices. From video, image, or audio processing, to telecommunications processing, many of these devices must perform several if not all of these tasks, often at the same time.

For example, a typical “smart” cell phone may require functionality to demodulate, decrypt, and decode incoming telecommunications signals, and encode, encrypt, and modulate outgoing telecommunication signals. If the smart phone also functions as an audio/video player, the smart phone may require functionality to decode and process the audio/video data. Similarly, if the smart phone includes a camera, the device may require functionality to process and store the resulting image data. Other functionality may be required for gaming, wired or wireless network connectivity, general-purpose computing, and the like. The device may be required to perform many if not all of these tasks simultaneously.

Similarly, a “home gateway” device may provide basic services such as broadband connectivity, Internet connection sharing, and/or firewall security. The home gateway may also perform bridging/routing and protocol and address translation between external broadband networks and internal home networks. The home gateway may also provide functionality for applications such as voice and/or video over IP, audio/video streaming, audio/video recording, online gaming, wired or wireless network connectivity, home automation, VPN connectivity, security surveillance, or the like. In certain cases, home gateway devices may enable consumers to remotely access their home networks and control various devices over the Internet.

Depending on the device, many of the tasks it performs may be processing-intensive and require some specialized hardware or software. In some cases, devices may utilize a host of different components to provide some or all of these functions. For example, a device may utilize certain chips or components to perform modulation and demodulation, while utilizing other chips or components to perform video encoding and processing. Other chips or components may be required to process images generated by a camera. This may require wiring together and integrating a significant amount of hardware and software.

Currently, there is no unified architecture or platform that can efficiently perform many or all of these functions, or at least be programmed to perform many or all of these functions. Thus, what is needed is a unified platform or architecture that can efficiently perform tasks such as data modulation, demodulation, encryption, decryption, encoding, decoding, transcoding, processing, analysis, or the like, for applications such as video, audio, telecommunications, and the like. Further needed is a unified platform or architecture that can be easily programmed to perform any or all of these tasks, possibly simultaneously. Such a platform or architecture would be highly useful in home gateways or other integrated devices, such as mobile phones, PDAs, video/audio players, gaming devices, or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific examples illustrated in the appended drawings. Understanding that these drawings depict only typical examples of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through use of the accompanying drawings, in which:

FIG. 1 is a high-level block diagram of one embodiment of a data processing architecture in accordance with the invention;

FIG. 2 is a high-level block diagram showing one embodiment of a group of clusters in the data processing architecture;

FIG. 3 is a high-level block diagram showing one embodiment of a cluster containing an array of processing elements (i.e., a VPU array);

FIG. 4 is a high-level block diagram of one embodiment of an array of processing elements inside the cluster;

FIG. 5 is a high-level block diagram showing various registers within the VPU array;

FIG. 6A is a high-level block diagram showing a VPC (vector processor unit controller) containing a grouping module and a modification module;

FIG. 6B is a more specific embodiment of a VPC wherein the grouping module includes a processing element (PE) map and the modification module includes an instruction modifier;

FIG. 7 is a high-level block diagram showing one embodiment of an address generation unit within a cluster;

FIG. 8 is a high-level block diagram showing additional details of an address generation unit in accordance with the invention;

FIG. 9A is a block diagram showing one embodiment of a “point-to-point” buffer;

FIG. 9B is a block diagram showing one embodiment of a “broadcast” buffer;

FIG. 9C is a block diagram showing one embodiment of a “scatter” buffer;

FIG. 9D is a block diagram showing one embodiment of a “gather” buffer;

FIG. 10 is a block diagram showing how vectors may be stored within a buffer;

FIG. 11A is a block diagram showing how a two-dimensional data structure may be stored in a buffer;

FIG. 11B is a block diagram showing the two-dimensional data structure of FIG. 1 A in two dimensions;

FIG. 11C is a block diagram showing one example of a FIFO access pattern for scanning a two-dimensional data structure;

FIG. 11D is a block diagram showing one example of a nested loop access pattern for scanning a two-dimensional data structure;

FIGS. 12A through 12E are block diagrams showing various access patterns for scanning two-dimensional data structures using matrix transforms; and

FIGS. 13A through 13K are block diagrams showing various access patterns for scanning two-dimensional data structures using end-point to end-point patterns.

DETAILED DESCRIPTION

The present invention provides a novel apparatus, system, and method for using nested loops to scan multi-dimensional data structures. The features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

In a first embodiment, a system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters (e.g., a starting offset, number of iterations for each loop, step size for each loop, etc.) defining the characteristics of the nested loops. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.

In another embodiment, a method in accordance with the invention may include providing a multi-dimensional data structure and providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining the characteristics of the nested loops. The method may then include accessing the data structure at the real addresses calculated by the address generation unit.

In another embodiment, an apparatus in accordance with the invention may include an address generation unit configured to calculate real addresses in order to access a data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the data structure. The address generation unit may receive as inputs a set of parameters defining the characteristics of the nested loops.

It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the apparatus and methods of the present invention, as represented in the Figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.

Many of the functional units described in this specification are shown as modules (or functional blocks) in order to emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

Modules may also be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose of the module.

Indeed, a module of executable code could be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, specific details may be provided, such as examples of programming, software modules, user selections, or the like, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods or components. In other instances, well-known structures, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

The illustrated embodiments of the invention will be best understood by reference to the drawings, wherein like parts are designated by like numerals throughout. The following description is intended only by way of example, and simply illustrates certain selected embodiments of apparatus and methods that are consistent with the invention as claimed herein.

Referring to FIG. 1, one embodiment of a data processing architecture 100 in accordance with the invention is illustrated. The data processing architecture 100 may be used to process (i.e., encode, decode, transcode, analyze, process) audio or video data although it is not limited to processing audio or video data. The flexibility and configurability of the data processing architecture 100 may also allow it to be used for tasks such as data modulation, demodulation, encryption, decryption, or the like, to name just a few. In certain embodiments, the data processing architecture may perform several of the above-stated tasks simultaneously as part of a data processing pipeline.

In certain embodiments, the data processing architecture 100 may include one or more groups 102, each containing one or more clusters of processing elements (as shown in FIGS. 2 and 3). By varying the number of groups 102 and/or the number of clusters within each group 102, the processing power of the data processing architecture 100 may be scaled up or down for different applications. For example, the processing power of the data processing architecture 100 may be considerably different for a home gateway device than it is for a mobile phone.

The data processing architecture 100 may also be configured to perform certain tasks (e.g., demodulation, decryption, decoding) simultaneously. For example, certain groups and/or clusters within each group may be configured for demodulation while others may be configured for decryption or decoding. In other cases, different clusters may be configured to perform different steps of the same task, such as performing different steps in a pipeline for encoding or decoding video data. The data processing architecture 100 may provide a unified platform for performing various tasks without the need for supporting hardware.

In certain embodiments, the data processing architecture 100 may include one or more processors 104, memory 106, memory controllers 108, interfaces 110, 112 (such as PCI interfaces 110 and/or USB interfaces 112), and sensor interfaces 114. A bus 116, such as a crossbar switch 116, may be used to connect the components together. A crossbar switch 116 may be useful because it provides a scalable interconnect that can mitigate possible throughput and contention issues.

In operation, data, such as video data, may be streamed through the interfaces 110, 112 into a data buffer memory 106. This data may be streamed from the data buffer memory 106 to group memories 206 (as shown in FIG. 2) and then to cluster memories 308 (as shown in FIG. 3), each forming part of a memory hierarchy. The groups and clusters will be described in more detail in FIGS. 2 and 3. In certain embodiments, a data pipeline may be created by streaming data from one cluster to another, with each performing a different function. After the data processing is complete, the data may be streamed out of the cluster memories 308 to the group memories 206, and then from the group memories 206 to the data buffer memory 106 and out one or more of the interfaces 110, 112.

A host processor 104 (e.g., a MIPS processor 104) may control and manage the actions of each of the components 102, 108, 110, 112, 114 and act as a supervisor for the data processing architecture 100. A sensor interface 114 may interface with various sensors (e.g., an IRDA sensor) which may receive commands from various control devices (e.g., a remote control). The host processor 104 may receive the commands from the sensor interface 114 and take appropriate action. For example, if the data processing architecture 100 is configured to decode television channels and the host processor 104 receives a command to begin decoding a particular television channel, the processor 104 may determine what the current loads of each of the groups 102 are and determine where to start a new process. For example, the host processor 104 may decide to distribute this new process over multiple groups 102, keep the process within a single group 102, or distribute it across all of the groups 102. In this way, the host processor 104 may perform load-balancing between the groups 102 and determine where particular processes are to be performed within the data processing architecture 100.

Referring to FIG. 2, one embodiment of a group 102 is illustrated. In general, a group 102 may be a semi-autonomous data processing unit that may include one or more clusters 200 of processing elements. The components of the group 102 may communicate over a bus 202, such as a crossbar switch 202. The internal components of the clusters 102 will be explained in more detail in association with FIG. 3. The group 102 may include one or more management processors 204 (e.g., MIPS processors 204), large local group memories 206 and associated memory controllers 208. A bridge 210 may connect the group 102 to the primary bus 116 illustrated in FIG. 1. Among other duties, the management processors 204 may perform load balancing across the clusters 200 and dispatch tasks to individual clusters 200 based on their availability. Prior to dispatching a task, the management processors 204 may, if needed, send parameters to the clusters 200 in order to program them to perform particular tasks. For example, the management processors 204 may send parameters to program an address generation unit, a cluster scheduler, or other components within the clusters 200, as shown in FIG. 3.

Referring to FIG. 3, in selected embodiments, a cluster 200 in accordance with the invention may include an array 300 of processing elements (i.e., a vector processing unit (VPU) array 300). An instruction memory 304 may store instructions associated with all the threads running on the cluster 200 and intended for the VPU array 300. A vector processor unit controller (VPC) 302 may fetch instructions from the instruction memory 304, decode the instructions, and transmit the decoded instructions to the VPU array 300 in a “modified SIMD” fashion. As will be explained in more detail in association with FIG. 6, the VPC 302 may act in a “modified SIMD” fashion by grouping particular processing elements and applying an instruction modified to each group. This may allow different processing elements to handle the same instruction differently. For example, this mechanism may be used to cause half of the processing elements to perform an ADD instruction while the other half performs a SUB instruction, all in response to a single instruction from the instruction memory 304. This feature adds a significant amount of flexibility and functionality to the cluster 200 as will be shown in more detail hereafter.

The VPC 302 may have associated therewith a scalar ALU 306 which may perform scalar algorithm computations, perform control-related functions, and manage the operation of the VPU array 300. For example, the scalar ALU 306 may reconfigure the processing elements by modifying the groups that the processing elements belong to or designating how the processing elements should handle instructions based on the group they belong to.

The cluster 200 may also include a data memory 308 storing vectors having a defined number (e.g., sixteen) of elements. In certain embodiments, the number of elements in each vector may be equal to the number of processing elements in the VPU array 300. Similarly, in selected embodiments, each vector element may include a defined number (e.g., sixteen) of bits. The number of bits in each element may be equal to the width (e.g., sixteen bits) of the data path between the data memory 308 and each processing element. It follows that if the data path between the data memory 308 and each processing element is 16-bits wide, the data ports (i.e., the read and write ports) to the data memory 308 may be 256-bits wide (16 bits for each of the 16 processing elements). These numbers are presented only by way of example are not intended to be limiting.

In selected embodiments, the cluster 200 may include an address generation unit 310 to generate real addresses when reading data from the data memory 308 or writing data back to the data memory 308. As will be explained in association with FIGS. 7 and 8, in selected embodiments, the address generation unit 310 may generate addresses in response to read/write requests from either the VPC 302 or connection manager 312 in a way that is transparent to the VPC 302 and connection manager 312. The cluster 200 may include a connection manager 312, communicating with the bus 202, whose primary responsibility is to transfer data into and out of the cluster 200.

In selected embodiments, instructions fetched from the instruction memory 304 may include a multiple-slot instruction (e.g., a three-slot instruction). For example, where a three-slot instruction is used, up to two (i.e., 0, 1, or 2) instructions may be sent to each processing element and up to one (i.e., 0 or 1) instruction may be sent to the scalar ALU 306. Instructions sent to the scalar ALU 306 may, for example, be used to change the grouping of processing elements, change how each group of processing elements should handle a particular instruction, or change the configuration of a permutation engine 318. In certain embodiments, the processing elements within the VPU array 300 may be considered parallel-semantic, variable-length VLIW (very long instruction word) processors, where the packet length is at least two instructions. Thus, in certain embodiments, the processing elements in the VPU array 300 may execute at least two instructions in parallel in a single clock cycle.

In certain embodiments, the cluster 200 may further include a parameter memory 314 to store parameters of various types. For example, the parameter memory 314 may store a processing element (PE) map to designate which group each processing element belongs to. The parameters may also include an instruction modifier designating how each group of processing elements should handle a particular instruction. In selected embodiments, the instruction modifier may designate how to modify at least one operand of the instruction, such as a source operand, destination operand, or the like. This concept will be explained in more detail in association with FIGS. 6A and 6B.

In selected embodiments, the cluster 200 may be configured to execute multiple threads simultaneously in an interleaved fashion. In certain embodiments, the cluster 200 may have a certain number (e.g., two) of active threads and a certain number (e.g., two) of dormant threads resident on the cluster 200 at any given time. Once an active thread has finished executing, a cluster scheduler 316 may determine the next thread to execute. In selected embodiments, the cluster scheduler 316 may use a Petri net or other tree structure to determine the next thread to execute, and to ensure that any necessary conditions are satisfied prior to dispatching a new thread. As previously mentioned, in certain embodiments, one or more of the group processors 204 (shown in FIG. 2) may program the cluster scheduler 316 with the appropriate Petri nets/tree structures prior to executing a program on the cluster 200.

Because a cluster 200 may execute and finish threads very rapidly, it is important that threads can be scheduled in an efficient maimer. In certain embodiments, an interrupt may be generated each time a thread has finished executing so that a new thread may be initiated and executed. Where threads are relatively short, the interrupt rate may become so high that thread scheduling has the potential to undesirably reduce the processing efficiency of the cluster 200. Thus, apparatus and methods are needed to improve scheduling efficiency and ensure that scheduling does not create bottlenecks in the system. To address this concern, in selected embodiments, the cluster scheduler 316 may be implemented in hardware as opposed to software. This may significantly increase the speed of the cluster scheduler 316 and ensure that new threads are dispatched in an expeditious manner. Nevertheless, in certain cases, the cluster hardware scheduler 316 may be bypassed and scheduling may be managed by other components (e.g., the group processor 204).

In certain embodiments, the cluster 200 may include permutation engine 318 to realign data that it read from or written to the data memory 308. The permutation engine 318 may be programmable to allow data to a reshuffled in a desired order before or after it is processed by the VPU array 300. In certain embodiments, the programming for the permutation engine 318 may be stored in the parameter memory 314. The permutation engine 318 may permute data having a width (e.g., 256 bits) corresponding to the width of the data path between the data memory 308 and the VPU array 300. In certain embodiments, the permutation engine 318 may be configured to permute data with a desired level of granularity. For example, the permutation engine 318 may reshuffle data on a byte-by-byte basis or other desired level of granularity.

Referring to FIG. 4, as previously mentioned, the VPU array 300 may include an array of processing elements, such as an array of sixteen processing elements (hereinafter labeled PE 0 through PE 15). As previously mentioned, these processing elements may simultaneously execute the same instruction on multiple data elements (i.e., a vector of data elements) in a “modified SIMD” fashion, as will be explained in more detail in FIGS. 6A and 6B. In the illustrated embodiment, the VPU array 300 includes sixteen processing elements arranged in a 4×4 array, with each processing element configured to process a sixteen bit data element. This arrangement of processing elements allows data to be passed between the processing elements in a specified manner as will be discussed in association with FIG. 5. Nevertheless, the VPU array 300 is not limited to a 4×4 array. Indeed, the cluster 200 may be configured to function with other n×n or even n×m arrays of processing elements, with each processing element configured to process a data element of a desired size.

Referring to FIG. 5, in selected embodiments, each of the processing elements of the VPU array 300 may include various registers to store data while it is being operated on. For example, the processing elements may include one or more internal general purpose registers 500 in which to store data. In addition, each of the processing elements may include one or more exchange registers 502 to transfer data between the processing elements. This may allow the processing elements to communicate with neighboring processing elements without the need to save the data to data memory 308 and then reload the data into internal registers 500.

For example, in selected embodiments, an exchange register 502 a may have a read port that is coupled to PE 0 and a write port that is coupled to PE 4, allowing data to be transferred from PE 4 to PE 0. Similarly, an exchange register 502 b may have a read port that is coupled to PE 4 and a write port that is coupled to PE 0, allowing data to be transferred from PE 0 to PE 4. This enables two-way communication between adjacent processing elements PE 0 and PE 4.

Similarly, for those processing elements on the edge of the array 300, the processing elements may be configured for “wrap-around” communication. For example, in selected embodiments, an exchange register 502 c may have a write port that is coupled to PE 0 and a read port that is coupled to PE 12, allowing data to be transferred from PE 0 to PE 12. Similarly, an exchange register 502 d may have a write port that is coupled to PE 12 and a read port that is coupled to PE 0, allowing data to be transferred from PE 12 to PE 0. Similarly, exchange registers 502 e, 502 f may enable two-way communication between processing elements PE 0 and PE 3 and exchange registers 502 g, 502 h may enable two-way communication between processing elements PE 0 and PE 1.

In certain embodiments, the cluster 200 may be configured such that data may be loaded from data memory 308 into either the internal registers 500 or the exchange registers 502 of the VPU array 300. The cluster 200 may also be configured such that data may be loaded from the data memory 308 into the internal registers 500 and exchange registers 502 simultaneously. Similarly, the cluster 200 may also be configured such that data may be transferred from either the internal registers 500 or the exchange registers 502 to data memory 308.

Referring to FIG. 6A, as previously mentioned, in selected embodiments, the VPU array 300 may be configured to act in a “modified SIMD” fashion. This may enable certain processing elements to be grouped together and the groups of processing elements to handle instructions differently. To provide this functionality, in selected embodiments, the VPC 302 may contain a grouping module 612 and a modification module 614. In general, the grouping module 612 may be used to assign each processing element within the VPU array 300 to one of several groups. A modification module 614 may designate how each group of processing elements should handle different instructions.

FIG. 6B shows one example of a method for implementing the grouping module 612 and modification module 614 of FIG. 6A. In selected embodiments, the grouping module 612 may include a PE map 602 to designate which group each processing element belongs to. This PE map 602 may, in certain embodiments, be stored in a register 600 on the VPC 302. This register 600 may be read by each processing element so that it can determine which group it belongs to. For example, in selected embodiments, the PE map 602 may store two bits for each processing element (e.g., 32 bits total for 16 processing elements), allowing each processing element to be assigned to one of four groups (groups 0, 1, 2, and 3). This PE map 602 may be updated as needed by the scalar ALU 306 to change the grouping.

In selected embodiments, the modification module 614 may include an instruction modifier 604 to designate how each group should handle an instruction 606. Like the PE map 602, this instruction modifier 604 may, in certain embodiments, be stored in a register 600 that may be read by each processing element in the array 300. For example, consider a VPU array 300 where the PE map 602 designates that PE 0 through PE 7 belong to “group 0” and PE 8 through PE 15 belong to “group 1.” An instruction modifier 604 may designate that group 0 should handle an ADD instruction as an ADD instruction, while group 1 should handle the ADD instruction as a SUB instruction. This will allow each group to handle the ADD instruction differently. Although the ADD instruction is used in this example, this feature may be used for a host of different instructions.

In certain embodiments, the instruction modifier 604 may also be configured to modify a source operand 608 and/or a destination operand 610 of an instruction 606. For example, if an ADD instruction is designed to add the contents of a first source register (R1) to the contents of a second source register (R2) and to store the result in a third destination register (R3), the instruction modifier 604 may be used to modify any or all of these source and/or destination operands. For example, the instruction modifier 604 for a group may modify the above-described instruction such that a processing element will use the source operand in the register (R5) instead of R1 and will save the destination operand in the destination register (R8) instead of R3. In this way, different processing elements may use different source and/or destination operands 608, 610 depending on the group they belong to.

Referring to FIG. 7, as previously mentioned, in selected embodiments, an address generation unit 310 may be used to generate real addresses in response to read/write requests from either the VPC 302 or the connection manager 312. In selected embodiments, the cluster 200 may be configured such that the VPC 302 and connection manager 312 make read or write requests to a “connection” 708 as opposed to specifying the real address 706 in data memory 308 where the read or write is to occur. This allows real addresses 706 to be generated in a way that is transparent to code in the instruction memory 304 and executed on the VPU array 300, thereby simplifying the writing of code for the cluster 200. That is, code that is executed by the VPU array 300 may read and write to “connections” 708 as opposed to real addresses 706 in data memory 308. The address generation unit 310 may be configured to translate the “connections” 708 into real addresses 706.

In selected embodiments, a “connection” 708 may be identified by a connection ID 700. Thus, whenever code attempts to read or write to the data memory 308, the code may identify a connection_ID 700 as opposed to a real address 706. In certain embodiments, the connection ID 700 may be composed of both a buffer_ID 702 and a port_ID 704. The buffer_ID 702 and port_ID 704 may correspond to a buffer and port, respectively. In general, the buffer may identify one or more regions in data memory 308 in which to read or write data. The port, on the other hand, may identify an access pattern for reading or writing data to the buffer. Various different types of buffers and ports will be explained in more detail in association with FIGS. 9A through 13K.

In selected embodiments, the connection_ID 700 may be made up of a pre-defined number of bits (e.g., sixteen bits). Accordingly, the buffer_ID 702 and port_ID 704 may use some portion of the pre-defined number of bits. For example, where the connection_ID 700 is sixteen bits, the buffer_ID 702 may make up the lower seven bits of the connection_ID 700 and the port_ID 704 may make up the upper nine bits of the connection_ID 700. This allows for 2⁷ (i.e., 128) buffers and 2⁹ (i.e., 512) ports.

Referring to FIG. 8, in selected embodiments, the address generation unit 310 may include various mechanisms for translating the connection_ID 700 into real addresses 706. For example, in certain embodiments, the address generation unit 310 may include a buffer descriptor memory 800 and a port descriptor memory 802. These memories 800, 802 may be two separate memory devices or the same memory device.

In selected embodiments, the buffer descriptor memory 800 may contain a buffer descriptor table 804 containing buffer records 808. In certain embodiments, the buffer records 808 are indexed by buffer_ID 702, although other indexing methods are also possible. Along with other information, the buffer records 808 may include a type 810, which may describe the type of buffer associated with the buffer_ID. In selected embodiments, buffer types may include but are not limited to “point-to-point,” “broadcast,” “scatter,” and “gather” buffer types, which will be explained in more detail in association with FIGS. 9A through 9D.

The buffer records 808 may also store attributes 812 associated with the buffers. These attributes 812 may include, among other information, the size of the buffer, a data available indicator (indicating whether data is available that may be read from the buffer), a space available indicator (indicating whether space is available in the buffer to write data), or the like. In selected embodiments, the buffer record 808 may also include a buffer base address 814. Using the buffer base address 814 and an offset 822 (as will be described in more detail hereafter), the address generation unit 310 may calculate real addresses in the data memory 308 when reading or writing thereto. The address generation unit 310 may generate the real addresses internally, eliminating the need for external code to specify real addresses for reading and writing.

Similarly, in selected embodiments, the port descriptor memory 802 may store a port descriptor table 806 containing port records 816. In certain embodiments, the port records 816 are also indexed by port_ID 704. In certain embodiments, the port records 816 may store a type 818, which may describe the type of port associated with the port_ID 704. In selected embodiments, port types may include but are not limited to “FIFO,” “matrix transform,” “nested loop,” “end point pattern” (EPP), and “non-recursive pattern” (NRP) port types, various of which will be explained in more detail in association with FIGS. 11A through 13K.

The port records 816 may also store attributes 820 of the ports they describe. These attributes 820 may vary depending on the type of port. For example, attributes 820 for a “nested loop” port may include, among other information, the number of times the nested loops are repeated, the step size of the loops, the dimensions of the two-dimensional data structure (to support wrapping in each dimension), or the like. Similarly, for an “end point pattern” port, the attributes 820 may include, among other information, the end points to move between when scanning the vectors in a buffer, the step size between the end points, and the like. Similarly, for a “matrix transform” port, the attributes 820 may include the matrix that is used to generate real addresses, or the like. The attributes 820 may also indicate whether the port is a “read” or “write” port.

In general, the attributes 820 may include the rules or parameters required to advance the offset 822 as vectors are read from or written to the buffer. The rules may follow either a “FIFO,” “matrix transform,” “nested loop,” “end point pattern” (EPP), or “non-recursive pattern” model, as previously discussed, depending on the type 818 of port. The offset 822 may be defined as the distance from the base address 814 of the buffer where data is read from or written to memory 308 (depending on whether the port is a “read” or “write” port). The offset 822 may be updated in the port descriptor 816 a when data is read from or written to the data memory 308 using the port 816 a. The address generation unit 310 may advance and keep track of the offset 822 internally, making it transparent to code executed on the VPU array 300.

Referring to FIGS. 9A through 9D, various embodiments of the “point-to-point,” “broadcast,” “scatter,” and “gather” buffers briefly described above are explained in more detail. FIG. 9A is a block diagram showing one example of a “point-to-point” buffer; FIG. 9B is a block diagram showing one example of a “broadcast” buffer; FIG. 9C is a block diagram showing one example of a “scatter” buffer; and FIG. 9D is a block diagram showing one example of a “gather” buffer. “Point-to-Point” Buffer

As illustrated in FIG. 9A, a point-to-point buffer may be generally defined as a buffer where there is a single producer (associated with a single write port) that writes data to a buffer 900, and a single consumer (associated with a single read port) that reads the data from the buffer 900 written by the producer. In selected embodiments, the consumer reads the data in the same order in which it was written to the buffer 900. In other embodiments, the consumer reads the data in a different order from which it was written to the buffer 900. For example, the read port of the consumer may be defined as a “FIFO” port, whereas the write port of the producer may be defined as a “nested loop” port. This may cause the consumer to read the data in a different pattern than it was written by the producer.

“Broadcast” Buffer

As shown in FIG. 9B, a broadcast buffer may be generally defined as a buffer 900 where each vector that is written to the buffer 900 by a single producer (with a single write port) may be broadcast to multiple consumers (each with a different read port). Stated otherwise, each vector that is written to the buffer 900 by a single producer may be consumed by multiple consumers. Nevertheless, in certain cases, although the consumers may read the same data from the same buffer, the consumers may be reading from different parts of the buffer at any given time.

“Scatter” Buffer

As shown in FIG. 9C, a scatter buffer may be generally defined as a buffer 900 in which vectors that are written to the buffer 900 by a single producer (with a single write port) may be “scattered” for consumption by multiple consumers (each with a different read port). In certain embodiments, a scatter buffer may be implemented by establishing several sub-buffers (or subdivisions) within a larger buffer 900. For example, if a producer writes three vectors to the larger buffer 900, the first vector may be written to a first sub-buffer, the second vector may be written to a second sub-buffer, and the third vector may be written to a third sub-buffer within the buffer 900. Vectors that are written to the first sub-buffer may be consumed by a first consumer, vectors that are written to the second sub-buffer may be consumed by a second consumer, and vectors that are written to the third sub-buffer may be consumed by a third consumer. Thus, this type of buffer 900 enables a producer to “scatter” vectors across various sub-buffers, each of which may be consumed by a different consumer. This is similar to the broadcast buffer except that each vector that is written to the buffer 900 is only consumed by a single consumer as opposed to multiple consumers. Thus, unlike the broadcast buffer, all the consumers do not share the same data.

“Gather” Buffer

As shown in FIG. 9D, a gather buffer may be generally defined as a buffer in which vectors generated by multiple producers may be gathered together into a single buffer. In certain embodiments, this type of buffer may also be implemented by establishing a number of sub-buffers within a larger buffer. For example, a first producer may be configured to write data to a first sub-buffer within the buffer, a second producer may be configured to write data to a second sub-buffer within the buffer, and a third producer may be configured to write data to a third sub-buffer within the buffer, A single consumer may be configured to consume the data produced by the multiple producers. In this way, data generated by multiple producers may be “gathered” together so that it may be consumed by a single or smaller number of consumers.

Referring to FIG. 10, as previously mentioned, a buffer 900 may identify one or more regions in data memory 308 in which to read or write data. A buffer 900 may store vectors 1000 (herein shown as vectors a₁₁, a₁₂, a₁₃, a₁₄) with each vector 1000 storing a defined number (e.g., sixteen) of elements, and each element storing a defined number (e.g., sixteen) of bits. The number of elements in each vector may be equal to the number of processing elements in the VPU array 300.

In selected applications, the buffer 900 may be used to store a multi-dimensional data structure, such as a two-dimensional data structure (e.g., two-dimensional video data). The VPU array 300 may operate on the multi-dimensional data structure. In such an embodiment, each of the vectors 1000 may represent some portion of the multi-dimensional data structure. For example, where the multi-dimensional data structure is a two-dimensional data structure, each of the vectors 1000 may represent a 4×4 block of pixels, where each element of a vector 1000 represents a pixel within the 4×4 block.

For example, referring to FIGS. 11A and 11B, consider a two-dimensional data structure stored in a buffer 900. Each vector 1000 in the buffer 900 may represent some portion of the two-dimensional data structure. In this example, each vector 1000 represents a 4×4 block of pixels, with each element of the vector 1000 representing a pixel within the 4×4 block. FIG. 11A shows the two-dimensional data structure stored in a buffer 900 in data memory 308. FIG. 11B shows the same two-dimensional data structure in two dimensions for illustration purposes. As shown in FIG. 11B, the 4×4 blocks 1102 of pixels are arranged in rows, with vectors a₁₁, a₁₂, a₁₂, . . . a_(1n), representing the 4×4 blocks of the first row, vectors a₂₁, a₂₂, a₂₃, . . . a_(2n) representing the 4×4 blocks of the second row, vectors a₃₁, a₃₂, a₃₃, . . . a_(3n) representing the 4×4 blocks of the third row, and so forth.

As previously mentioned, different “ports” may be used to access (i.e., read and/or write) data in a buffer 900 in different patterns. It has been found that processing video data may require the data to be accessed in different patterns. Some of these ports, more particularly the “FIFO,” “nested loop,” “matrix transform,” and “end point pattern” ports previously discussed, will be explained in more detail in association with FIGS. 11C through 13K. In general, a port type may be selected based on the desired access pattern.

“FIFO” port

An access pattern for a FIFO port (also known as “raster scan” access) may simply include an address increment with wrap around. For example, referring to FIG. 11C, an access pattern using a FIFO port may traverse the following path of the n×m two-dimensional data structure 1100: a₁₁, a_(12, a) ₁₃, . . . a_(1n), a₂₁, a₂₂, a₂₃, . . . a_(2n), a₃₁, a₃₂, a₃₃, . . . a_(3n), and so forth. When the access pattern reaches the end of the buffer 900, it may wrap around to access the first address in the buffer 900.

“Nested Loop” Port

FIG. 11D shows one example of a pattern for accessing an n×m two-dimensional data structure 1100 using a “nested loop” port. This access pattern may be generated using a series of nested loops associated with a “nested loop” port. The port and associated nested loops (including the jumps (step size) and number of iterations for each loop) may be pre-programmed into the address generation unit as part of a port descriptor prior to accessing the two-dimensional data structure 1100. As shown in FIG. 11D, the access pattern follows the substantially zig-zag path (i.e, a₁₁, a₂₁, a₁₂, a₂₂, a₁₃, a₂₃, . . . a_(1n), a_(2n), a₃₁, a₄₁, etc.). After setting the initial offset in the buffer to a₁₁, the access pattern may be generated in the address generation unit 310 using the following nested loops:

inner loop: jump by n (loops 1 time)

intermediate loop: jump by 1 (loops n times)

outer loop: jump by 2n (loops m/2 times)

In the above example, the loops do not inherit the starting points of the previous loops. However, in other embodiments, the loops may be configured to inherit the starting points of the previous loops. The parameters (i.e, the step-size and number of iterations for each loop) of the nested loops may be varied to generate various types of access patterns. Thus, the access pattern shown in FIG. 11D represents just one exemplary access pattern and is not intended to be limiting.

“Matrix Transform” Port

Ports having the matrix port type may have a counter multiplied by a transform matrix to determine a buffer offset 822. The matrix multiplication of a FIFO pointer (or simple counter) by a transform matrix creates a new programmable access pattern. An 8-bit offset may require a 64-entry transform matrix, where each entry is one bit. Since the matrix elements are single bits, the multiplication reduces to an AND operation, while the addition reduces to an XOR operation as shown in the equation below. The port descriptor may contain both the offset information as well as the transform matrix.

${{\begin{bmatrix} t_{11} & t_{12} & \ldots & t_{1\; N} \\ t_{21} & \; & \; & \; \\ \ldots & \; & \; & \; \\ t_{N\; 1} & \; & \; & t_{NN} \end{bmatrix} \times \begin{bmatrix} a_{1} \\ a_{2} \\ \ldots \\ a_{N} \end{bmatrix}} + \begin{bmatrix} b_{1} \\ b_{2} \\ \ldots \\ b_{N} \end{bmatrix}} = {\quad\begin{bmatrix} {\left( {{t_{11}\&}\mspace{14mu} a_{1}} \right)\hat{}{\left( {{t_{12}\&}\mspace{14mu} a_{2}} \right)\hat{}{{\ldots \left( {{t_{1\; N}\&}\mspace{14mu} a_{N}} \right)}\hat{}b_{1}}}} \\ {\left( {{t_{21}\&}\mspace{14mu} a_{1}} \right)\hat{}{\left( {{t_{22}\&}\mspace{14mu} a_{2}} \right)\hat{}{{\ldots \left( {{t_{2\; N}\&}\mspace{14mu} a_{N}} \right)}\hat{}b_{2}}}} \\ \ldots \\ {\left( {{t_{N\; 1}\&}\mspace{14mu} a_{1}} \right)\hat{}{\left( {{t_{N\; 2}\&}\mspace{14mu} a_{2}} \right)\hat{}{{\ldots \left( {{t_{NN}\&}\mspace{14mu} a_{N}} \right)}\hat{}b_{N}}}} \end{bmatrix}}$

The matrix transform may be used to support recursive access patterns such as U-order (FIG. 12A), N-order (FIG. 12B), X-order (FIG. 12C), Z-order (FIG. 12D), and Gray-order (FIG. 12E) access patterns. The access patterns shown in FIGS. 12A through 12E are examples of patterns that may be generated with the matrix transform port and are not intended to be limiting.

“End-Point Pattern” Port

Ports having the “end-point pattern” type may be used to support non-recursive access patterns such as the wiper scan (FIG. 13A), diagonal (zigzag) scan D (FIG. 13B), raster scan R (FIG. 13C), vertical continuous wiper scan (FIG. 13D), spiral scan S (FIG. 13E), horizontal continuous raster scan C (FIG. 13F), right orthogonal (FIG. 13G), diagonal symmetry Y (FIG. 13H), horizontal symmetry M (FIG. 131), diagonal parallel E (FIG. 13J), and diagonal secondary W (FIG. 13K). These patterns may be derived by establishing end points, and then moving between the end points to generate a desired access pattern. These patterns represent just a few patterns that are possible using the “end-point pattern” port, and are not intended to be limiting.

For example, referring to the access pattern of FIG. 13E, consider an initial set of end points 1300 a, 1302 a, 1304 a, 1306 a. The access pattern may be generated by initially moving from a first end point 1300 a to a second end point 1302 a, and then from the second end point 1302 a to a third end point 1304 a, and then from the third end point 1304 a to a fourth end point 1306 a. These end points 1300 a, 1302 a, 1304 a, 1306 a may then be moved or modified (by program code or other means) to new locations to continue the pattern. For example, the first end point 1300 a may be moved to a fifth end point 1300 b; a second end point 1302 a may be moved to a sixth end point 1302 b; a third end point 1304 a may be moved to a seventh end point 1304 b; and a fourth end point 1306 a may be moved to an eighth end point 1306 b. The pattern may then continue by moving from the fourth end point 1306 a to the fifth end point 1300 b, from the fifth end point 1300 b to the sixth end point 1302 b, from the sixth end point 1302 b to the seventh end point 1304 b, and from the seventh end point 1304 b to the eighth end point 1306 b, and so forth. This process may continue until the access pattern of FIG. 13E is generated. A certain step-size or jump between vectors may be defined when moving between endpoints. The end points and the jumps or step-size between end points may be programmed into the port descriptor associated with the “end point pattern” port.

The “end-point pattern” port type is useful to generate many access patterns that may be difficult or impossible to generate using other port types. This algorithm may also be useful in many mathematical operations, particularly faster search algorithms to improve encoding efficiency.

“Non-Recursive Pattern” Port

This type of port may be used to support non-recursive access patterns that are not achievable or supported using the matrix transform port or other types of ports. In general, the “non-recursive pattern” port may be similar to the “nested loop” port except that it may use consecutive loops (i.e., sequential loops) instead of nested loops to generate addresses.

The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. 

1. A system comprising: a data memory storing a multi-dimensional data structure; an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern; the address generation unit further configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure, the address generation unit receiving as inputs a set of parameters defining the characteristics of the nested loops; and a processor configured to access the data structure at the real addresses calculated by the address generation unit.
 2. The system of claim 1, wherein access includes at least one of reads and writes to the multi-dimensional data structure.
 3. The system of claim 1, wherein the processor is a vector processor.
 4. The system of claim 1, wherein the multi-dimensional data structure is a two-dimensional data structure.
 5. The system of claim 1, wherein the multi-dimensional data structure is stored in a buffer in the data memory.
 6. The system of claim 5, wherein the parameters include a starting offset within the buffer to calculate an initial real address.
 7. The system of claim 1, wherein the parameters include the number of iterations for the loops within the nested loops.
 8. The system of claim 1, wherein the parameters include at least one of the step size for the loops within the nested loops, the dimensions of the multi-dimensional data structure, and the inheritance between the loops of the nested loops.
 9. A method comprising: providing a multi-dimensional data structure; providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern; configuring the address generation unit to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure, the address generation unit receiving as inputs a set of parameters defining the characteristics of the nested loops; and accessing the data structure at the real addresses calculated by the address generation unit.
 10. The method of claim 9, wherein accessing the multi-dimensional data structure includes at least one of reading from and writing to the multi-dimensional data structure.
 11. The method of claim 9, wherein accessing the multi-dimensional data structure includes accessing the data structure with a vector processor.
 12. The method of claim 9, wherein the multi-dimensional data structure is a two-dimensional data structure.
 13. The method of claim 9, wherein providing a multi-dimensional data structure comprises storing the multi-dimensional data structure in a buffer in data memory.
 14. The method of claim 13, wherein the parameters include a starting offset within the buffer to calculate an initial real address.
 15. The method of claim 9, wherein the parameters include the number of iterations for loops within the nested loops.
 16. The method of claim 9, wherein the parameters include at least one of the step size for the loops within the nested loops, the dimensions of the multi-dimensional data structure, and the inheritance between the loops of the nested loops.
 17. An apparatus comprising: an address generation unit configured to calculate real addresses in order to access a data structure in a desired pattern; and the address generation unit further configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the data structure, the address generation unit receiving as inputs a set of parameters defining the characteristics of the nested loops.
 18. The apparatus of claim 17, wherein access includes at least one of reads and writes to the data structure.
 19. The apparatus of claim 17, further comprising a processor to access the data structure at the real addresses calculated by the address generation unit.
 20. The apparatus of claim 17, further comprising a buffer in data memory to store the data structure.
 21. The apparatus of claim 20, wherein the parameters include a starting offset within the buffer to calculate an initial real address.
 22. The apparatus of claim 17, wherein the parameters include the number of iterations for the loops within the nested loops.
 23. The apparatus of claim 17, wherein the parameters include at least one of the step size for the loops within the nested loops, the dimensions of the multi-dimensional data structure, and the inheritance between the loops of the nested loops. 